9T Full Adder Design in Subthreshold Region
نویسندگان
چکیده
منابع مشابه
Design of Low Power 9T Full Adder Based 4*4 Wallace Tree Multiplier
Multiplier is an important key element used for arithmetic operations in digital signal processor. Power consumption in multiplier is more when compared with adders and subtractors. So reducing the power consumption of multiplier makes a digital signal processor more efficient. A Wallace tree multiplier is an efficient high speed multiplier that multiplies two integers. Here a 4*4 Wallace tree ...
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ژورنال
عنوان ژورنال: VLSI Design
سال: 2012
ISSN: 1065-514X,1563-5171
DOI: 10.1155/2012/248347